US 12,467,974 B2
Diagnostic ring oscillator circuit for DC and transient characterization
Andreas Kerber, Pleasanton, CA (US); and Phillip Kliza, Palo Alto, CA (US)
Assigned to INTEL NDTM US LLC, Santa Clara, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Dec. 26, 2023, as Appl. No. 18/396,111.
Claims priority of provisional application 63/535,044, filed on Aug. 28, 2023.
Prior Publication US 2024/0133952 A1, Apr. 25, 2024
Int. Cl. G01R 31/28 (2006.01); G01R 31/26 (2020.01); G01R 31/319 (2006.01); H03K 3/03 (2006.01); H03K 3/354 (2006.01); H03K 17/687 (2006.01); H03K 19/0185 (2006.01)
CPC G01R 31/31915 (2013.01) [G01R 31/2626 (2013.01); G01R 31/31905 (2013.01); H03K 3/0315 (2013.01); H03K 3/354 (2013.01); H03K 17/6872 (2013.01); H03K 19/018521 (2013.01); H03K 2217/0054 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An in situ ring oscillator (RO) circuit for capturing one or more characteristic relating to aging of CMOS circuitry in a CMOS device, comprising:
a plurality of symmetrical stages coupled via an RO feedback signal line and forming an inverter chain, the plurality of symmetrical stages including, for each stage, a CMOS inverter comprising a pair of pMOS and nMOS transistors coupled between first and second power-gating transistors respectively coupled to a positive voltage source and ground, wherein an output of the CMOS inverter for the stage is coupled to an input for the CMOS inverter of a next stage;
wherein the plurality of symmetrical stages include at least:
an enable stage configured to enable the inverter chain to be put into a defined logic state or mode;
one or more Device Under Test (DUT) stages, each having a gate of the first power-gating transistor coupled to a DUT header, and a gate of the second power-gating transistor coupled to a DUT footer; and
a pre-stage, preceding each of the one or more DUT stages.