US 12,467,945 B2
Test board and method for testing semiconductor device
Hideaki Murakami, Saitama Saitama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 30, 2022, as Appl. No. 17/898,998.
Claims priority of application No. 2022-028395 (JP), filed on Feb. 25, 2022.
Prior Publication US 2023/0273239 A1, Aug. 31, 2023
Int. Cl. G01R 1/04 (2006.01); G01R 31/28 (2006.01)
CPC G01R 1/0466 (2013.01) [G01R 1/0483 (2013.01); G01R 31/2879 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A test board comprising:
a substrate;
a socket mounted on the substrate and including a first connector pin to be connected to a first terminal of a semiconductor device when the semiconductor device is mounted in the socket;
a plurality of external terminals through which a voltage or a signal is supplied to the first connector pin;
a first current path that is electrically connectable between the first connector pin and one of the plurality of external terminals, and includes a first circuit element;
a second current path that is electrically connectable between the first connector pin and one of the plurality of external terminals, and includes no circuit element or a second circuit element different from the first circuit element; and
a first connection mechanism capable of electrically connecting the first connector pin to one of the plurality of external terminals via one of the first current path and the second current path, wherein the first connection mechanism includes
a first jumper pin electrically connected to the first connector pin via the first current path,
a second jumper pin electrically connected to the first connector pin via the second current path,
a third jumper pin electrically connectable to one of the plurality of external terminals,
a first jumper plug including a first part connectable to the first jumper pin or the second jumper pin, and a second part connectable to the third jumper pin,
a fourth jumper pin electrically connected to one of the plurality of external terminals,
a fifth jumper pin electrically connected to another one of the plurality of external terminals,
a sixth jumper pin electrically connected to the third jumper pin, and
a second jumper plug including a third part connectable to the fourth jumper pin or the fifth jumper pin, and a fourth part connectable to the sixth jumper pin.