| CPC B81C 1/00396 (2013.01) [B81B 3/0005 (2013.01); B81B 3/0081 (2013.01); B81B 7/0038 (2013.01); B81B 7/007 (2013.01); B81B 7/02 (2013.01); B81C 1/00269 (2013.01); B81C 1/00992 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2203/0315 (2013.01); B81B 2203/04 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0119 (2013.01); B81C 2201/013 (2013.01); B81C 2201/0132 (2013.01); B81C 2201/014 (2013.01); B81C 2201/0147 (2013.01); B81C 2201/0159 (2013.01); B81C 2201/016 (2013.01); B81C 2201/019 (2013.01); B81C 2201/0198 (2013.01); B81C 2201/112 (2013.01); B81C 2203/0109 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/019 (2013.01); B81C 2203/035 (2013.01); B81C 2203/036 (2013.01)] | 33 Claims |
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1. A method comprising:
depositing a bonding material on a first, a second, and a third portions of a substrate, wherein the first, the second and the third portions are associated with a first, a second, and a third standoff regions;
depositing and patterning a mask over a fourth portion of the substrate that is exposed and further on the bonding material, wherein a first exposed portion of the patterned mask is associated with a first cavity region positioned between the first and the second standoff regions and a second exposed portion of the patterned mask is associated with a second cavity region positioned between the second and the third standoff regions;
depositing and patterning a photoresist mask over the patterned mask to expose at least two regions within the first cavity region;
etching the at least two regions to form a first cavity;
removing a remainder of the photoresist mask to expose the first cavity region and the second cavity region;
etching the first cavity region and the second cavity region, wherein the etching the first cavity region increases a depth of the first cavity and wherein the etching the second cavity region forms a second cavity between the second and the third standoff regions, and wherein a depth of the first cavity region within the first cavity is greater than a depth of the second cavity;
depositing and patterning a getter material to cover a portion of the first cavity; and
removing the patterned mask to expose the bonding material.
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19. A method comprising:
depositing an intermetal dielectric (IMD) layer over a substrate;
forming a first mask over the IMD layer;
patterning the first mask to form a patterned first mask, wherein a first exposed portion of the patterned first mask is associated with a first cavity region positioned between a first and a second standoff regions and a second exposed portion of the patterned mask is associated with a second cavity region positioned between the second and a third standoff regions, and wherein the patterned first mask covers the first, the second, and the third standoff regions;
etching exposed portions of the IMD layer based on the patterned first mask to form a first cavity within the first cavity region and a second cavity within the second cavity region and further to form a first, a second, and a third standoff associated with the first, the second, and the third standoff regions respectively;
forming a second mask over the patterned first mask and further over exposed portions of the IMD layer;
patterning the second mask to form a patterned second mask, wherein the patterned second mask covers a region associated with a first bumpstop within the first cavity and a region associated with a second bumpstop within the second cavity, and wherein the patterned second mask further covers the first, the second, and the third standoff regions;
etching exposed portions of the IMD based on the patterned second mask to form the first bumpstop and the second bumpstop;
removing the patterned second mask;
depositing a polysilicon layer over the patterned first mask and further in the first cavity and the second cavity and the first and the second bumpstops;
forming a getter material over the polysilicon layer;
patterning the getter material to cover a portion of the polysilicon layer within the first cavity;
patterning the polysilicon layer that is exposed, wherein patterning the polysilicon layer exposes a portion of the IMD layer within the first cavity and the second cavity while covering the first and the second bumpstops; and
forming a bonding material over the polysilicon layer on the first, the second, and the third standoffs.
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