US 12,137,621 B2
Intercalated metal/dielectric structure for nonvolatile memory devices
Mauricio Manfrini, Zhubei (TW); Chung-Te Lin, Tainan (TW); Gerben Doornbos, Kessel-Lo (BE); and Marcus Johannes Henricus van Dal, Linden (BE)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 16, 2023, as Appl. No. 18/336,088.
Application 18/336,088 is a continuation of application No. 17/218,324, filed on Mar. 31, 2021.
Application 17/218,324 is a continuation of application No. 16/412,810, filed on May 15, 2019, granted, now 10,971,684, issued on Apr. 6, 2021.
Claims priority of provisional application 62/752,571, filed on Oct. 30, 2018.
Prior Publication US 2023/0337557 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/04 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/823 (2023.02) [G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); H10B 63/30 (2023.02); H10N 70/021 (2023.02); H10N 70/841 (2023.02); H10N 70/883 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a bottom electrode disposed over a monocrystalline silicon or silicon-on-insulator substrate;
an intercalated metal and dielectric stack over the bottom electrode;
a chalcogenide layer over the intercalated metal and dielectric stack; and
a top electrode over the chalcogenide layer.