US 12,137,619 B2
Reducing qubit frequency collisions through lattice design
Jerry M. Chow, White Plains, NY (US); Easwar Magesan, Mount Kisco, NY (US); Matthias Steffen, Cortlandt Manor, NY (US); Jay M. Gambetta, Yorktown Heights, NY (US); and Maika Takita, Croton-on-Hudson, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 1, 2021, as Appl. No. 17/515,686.
Application 17/515,686 is a division of application No. 16/751,429, filed on Jan. 24, 2020, granted, now 11,165,009.
Application 16/751,429 is a division of application No. 15/934,457, filed on Mar. 23, 2018, granted, now 10,622,536, issued on Apr. 14, 2020.
Prior Publication US 2022/0059749 A1, Feb. 24, 2022
Int. Cl. H10N 60/80 (2023.01); G06N 10/00 (2022.01); H10N 60/12 (2023.01)
CPC H10N 60/805 (2023.02) [G06N 10/00 (2019.01); H10N 60/12 (2023.02)] 23 Claims
OG exemplary drawing
 
1. A quantum processing device comprising:
qubits arranged in a lattice arrangement, in which the lattice arrangement comprises:
adjacent structures having vertices connected by edges, wherein the qubits are positioned on the vertices, and wherein each of the qubits in the lattice arrangement connects to, thereby being directly adjacent to, with no intervening elements, not more than three other qubits such that a connectivity of each of the qubits to other ones of neighboring qubits, by arranging the qubits with the lattice arrangement, lowers a likelihood of a frequency collision between neighboring ones of the qubits.