US 12,137,618 B2
Stacked die assembly
Arnaud Laville, Neuchatel (CH); Eric Lahaye, Nandrin (BE); and Jian Chen, Heist-op-den-Berg (BE)
Assigned to MELEXIS TECHNOLOGIES SA, Bevaix (CH)
Filed by Melexis Technologies SA, Bevaix (CH)
Filed on Jul. 13, 2023, as Appl. No. 18/351,797.
Application 18/351,797 is a continuation of application No. 17/065,004, filed on Oct. 7, 2020, granted, now 11,849,650.
Claims priority of application No. 19202699 (EP), filed on Oct. 11, 2019.
Prior Publication US 2023/0371401 A1, Nov. 16, 2023
Int. Cl. H10N 52/80 (2023.01); G01R 33/07 (2006.01); H01L 23/495 (2006.01); H01L 25/065 (2023.01); H10N 52/00 (2023.01)
CPC H10N 52/80 (2023.02) [G01R 33/07 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 25/0657 (2013.01); H10N 52/101 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A sensor device comprising:
a lead frame;
a first semiconductor die having a first rectangular shape with a first geometrical center, and being electrically connected to the lead frame, and comprising a first sensor structure situated at a first sensor location;
a second semiconductor die having a second rectangular shape, and having a second geometrical center, and being electrically connected to the lead frame, and comprising a second sensor structure situated at a second sensor location;
wherein:
the first rectangular shape has a length defining a length direction, and a width defining a width direction perpendicular to the length direction, said length being equal to or larger than said width;
the first sensor location is offset from the first geometrical center by a first predetermined offset along the length direction, and/or by a second predetermined offset in the width direction;
at least one of the first and second predetermined offset is different from zero;
an orthogonal projection of the first and the second sensor location onto the lead frame coincide; and
the second semiconductor die is stacked with the first semiconductor die, and is rotated by 90° or by 180° with respect to the first semiconductor die about an imaginary axis perpendicular to the lead frame; and
wherein the first semiconductor die is implemented in a first CMOS technology node and the second semiconductor die is implemented in a second CMOS technology node different from the first CMOS technology node.