US 12,137,574 B2
Integration of ferroelectric memory devices having stacked electrodes with transistors
Sasikanth Manipatruni, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); Ramamoorthy Ramesh, Moraga, CA (US); Gaurav Thareja, Santa Clara, CA (US); and Amrita Mathuriya, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Aug. 15, 2023, as Appl. No. 18/357,974.
Application 18/357,974 is a continuation of application No. 17/663,187, filed on May 12, 2022, granted, now 11,758,738.
Application 17/663,187 is a continuation of application No. 16/729,273, filed on Dec. 27, 2019, granted, now 11,289,497, issued on Mar. 29, 2022.
Prior Publication US 2024/0099018 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); G11C 11/22 (2006.01); H01L 49/02 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 11/221 (2013.01); H01L 28/56 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a pair of transistors, wherein a first transistor in the pair of transistors and a second transistor in the pair of transistors comprise:
a source region;
a drain region;
a gate electrode between the source region and the drain region;
a word line coupled with the gate electrode;
a drain contact coupled with the drain region; and
a first via coupled with the drain contact;
a first ferroelectric structure electrically coupled with the first via of the first transistor;
a second ferroelectric structure electrically coupled with the first via of the second transistor, wherein the first ferroelectric structure and the second ferroelectric structure respectively comprise:
a second via comprising a fill metal within a first discontinuity in an etch stop layer, and within a second discontinuity in an interlayer dielectric (ILD) over the etch stop layer, wherein the second via is on the first via;
a capacitor on at least a portion of the fill metal, the capacitor comprising:
a stack of bottom electrode layers, wherein a lowermost bottom electrode layer in the stack of bottom electrode layers is in contact with the first via;
a dielectric layer comprising a non-linear polar dielectric material having a form ABOX, wherein A and B are two different cations, and wherein X is 1, 2, or 3 on an uppermost bottom electrode layer in the stack of bottom electrode layers;
a stack of top electrode layers, wherein a lowermost top electrode layer in the stack of top electrode layers is in contact with the dielectric layer;
an encapsulation layer comprising at least oxygen or nitrogen on sidewalls of the capacitor but not on a sidewall of the lowermost bottom electrode layer;
a metal contact on a topmost top electrode layer in the stack of top electrode layers;
a third via coupled with the source region of the first transistor or the source region of the second transistor, wherein the source region of the first transistor is coupled with the source region of the second transistor; and
a bit line coupled with the third via.