US 12,137,573 B2
Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same
Gao-Ming Wu, Taipei (TW); Katherine H. Chiang, New Taipei (TW); Chien-Hao Huang, Hsinchu (TW); and Chung-Te Lin, Taiwan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Mar. 17, 2022, as Appl. No. 17/697,101.
Claims priority of provisional application 63/287,741, filed on Dec. 9, 2021.
Prior Publication US 2023/0189533 A1, Jun. 15, 2023
Int. Cl. H10B 53/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H10B 53/30 (2023.02) [H10B 61/22 (2023.02); H10B 63/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, comprising:
forming a two-dimensional array of discrete dielectric template structures over a substrate, wherein the discrete dielectric template structures are spaced from one another by trenches;
forming a first dielectric spacer matrix layer by depositing a first dielectric spacer material in lower portions of the trenches;
forming a second dielectric spacer matrix layer by depositing a second dielectric spacer material in upper portions of the trenches;
forming a pair of a source cavity and a drain cavity within a volume of each of the discrete dielectric template structures;
forming a source electrode and a drain electrode in each source cavity and each drain cavity, respectively; and
forming gate electrodes prior to, or after, formation of the two-dimensional array of discrete dielectric template structures, whereby a two-dimensional array of field effect transistors is formed.