US 12,137,572 B2
Ferroelectric memory device and method of manufacturing the same
Yi Yang Wei, Hsinchu (TW); Tzu-Yu Lin, Hsinchu (TW); Bi-Shen Lee, Hsinchu (TW); Hai-Dang Trinh, Hsinchu (TW); Hsing-Lien Lin, Hsin-Chu (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 26, 2021, as Appl. No. 17/385,576.
Claims priority of provisional application 63/154,038, filed on Feb. 26, 2021.
Prior Publication US 2022/0278115 A1, Sep. 1, 2022
Int. Cl. H10B 53/30 (2023.01); H01L 49/02 (2006.01)
CPC H10B 53/30 (2023.02) [H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a ferroelectric stack having:
a first electrode and a second electrode;
a first ferroelectric layer and a second ferroelectric layer disposed between the first electrode and the second electrode, wherein the first ferroelectric layer and the second ferroelectric layer include a first dielectric material;
a dielectric layer disposed between the first ferroelectric layer and the second ferroelectric layer, wherein the dielectric layer includes a second dielectric material that is different than the first dielectric material; and
wherein the first dielectric material has a crystalline structure having orthorhombic crystalline phase (O-phase) portions and monoclinic crystalline phase (M-phase) portions, wherein a volume of the M-phase portions in the first dielectric material is less than about 10%.