US 12,137,571 B2
Integrated circuit including three-dimensional memory device
Bo-Feng Young, Taipei (TW); Yi-Ching Liu, Hsinchu (TW); Sai-Hooi Yeong, Hsinchu County (TW); Yih Wang, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 21, 2023, as Appl. No. 18/516,908.
Application 18/516,908 is a continuation of application No. 17/347,596, filed on Jun. 15, 2021, granted, now 11,856,786.
Claims priority of provisional application 63/153,965, filed on Feb. 26, 2021.
Prior Publication US 2024/0090231 A1, Mar. 14, 2024
Int. Cl. H10B 51/40 (2023.01); G11C 11/22 (2006.01); H01L 23/522 (2006.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 51/50 (2023.01)
CPC H10B 51/40 (2023.02) [G11C 11/2257 (2013.01); H01L 23/5226 (2013.01); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 51/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a three-dimensional memory device, comprising stacking structures laterally extending along a column direction, wherein each of the stacking structure comprises alternately stacked word lines and isolation layers, and the stacking structures are shaped into first staircase structures and second staircase structures at first and second sides of the three-dimensional memory device, respectively;
a first word line driving circuit, positioned below and overlapped with the first staircase structures, and comprising an array of first transistors, wherein a first group of the word lines in one of the stacking structures are connected to a column of the first transistors arranged along the column direction; and
a second word line driving circuit, positioned below and overlapped with the second staircase structures, and comprising an array of second transistors, wherein a second group of the word lines in the one of the stacking structures are connected to a column of the second transistors arranged along the column direction.