US 12,137,570 B2
Three dimensional memory device
Chia-Ta Yu, New Taipei (TW); Chia-En Huang, Xinfeng Township (TW); Yi-Ching Liu, Hsinchu (TW); Yih Wang, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 30, 2021, as Appl. No. 17/566,313.
Claims priority of provisional application 63/172,934, filed on Apr. 9, 2021.
Prior Publication US 2022/0328502 A1, Oct. 13, 2022
Int. Cl. H10B 51/30 (2023.01); H10B 51/20 (2023.01)
CPC H10B 51/30 (2023.02) [H10B 51/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a three dimensional memory array comprising a plurality of memory cells arranged in a three-dimensional array extending in a first (x), second (y) and third (z) dimensions in a plurality of rows and a plurality of columns, wherein each of the plurality of columns are associated with a bit line and a select line; and
a plurality of select gate pairs, each of the plurality of select gate pairs being associated with a column of the plurality of columns, wherein each of the plurality of select gate pairs comprises a first select gate and a second select gate, wherein the bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column, wherein the select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column, and wherein the plurality of select gate pairs are formed in a layer above the plurality of memory cells.