US 12,137,569 B2
Memory device and method of forming the same
Chao-I Wu, Hsinchu County (TW); Yu-Ming Lin, Hsinchu (TW); Shih-Lien Linus Lu, Hsinchu (TW); Sai-Hooi Yeong, Hsinchu County (TW); and Bo-Feng Young, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 31, 2023, as Appl. No. 18/162,642.
Application 18/162,642 is a continuation of application No. 17/228,671, filed on Apr. 12, 2021, granted, now 11,587,950.
Claims priority of provisional application 63/047,243, filed on Jul. 1, 2020.
Prior Publication US 2023/0189529 A1, Jun. 15, 2023
Int. Cl. H10B 51/20 (2023.01); H01L 29/24 (2006.01); H10B 43/20 (2023.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/24 (2013.01); H10B 43/20 (2023.02); H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a memory device, comprising:
forming a first cell region in a first multi-layer stack, wherein the first cell region comprises stacks of first ferroelectric field effect transistors (FeFETs) with a first electron mobility, and the first multi-layer stack comprises alternately stacked first word lines and first dielectric layers; and
forming a second cell region in a second multi-layer stack, wherein the second cell region comprises stacks of second FeFETs with a second electron mobility greater than the first electron mobility, the second multi-layer stack comprises alternately stacked second word lines and second dielectric layers, and the second multi-layer stack is laterally adjacent to and substantially in parallel with the first multi-layer stack.