US 12,137,568 B2
Hybrid bonding contact structure of three-dimensional memory device
Zhenyu Lu, Wuhan (CN); Simon Shi-Ning Yang, Wuhan (CN); Feng Pan, Wuhan (CN); Steve Weiyi Yang, Wuhan (CN); Jun Chen, Wuhan (CN); Guanping Wu, Wuhan (CN); Wenguang Shi, Wuhan (CN); and Weihua Cheng, Wuha (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 12, 2023, as Appl. No. 18/221,358.
Application 18/221,358 is a continuation of application No. 18/052,459, filed on Nov. 3, 2022, granted, now 11,758,732.
Application 18/052,459 is a continuation of application No. 17/148,209, filed on Jan. 13, 2021, granted, now 11,527,547, issued on Dec. 13, 2022.
Application 17/148,209 is a continuation of application No. 16/821,757, filed on Mar. 17, 2020, granted, now 10,923,491, issued on Feb. 16, 2021.
Application 16/821,757 is a continuation of application No. 16/046,852, filed on Jul. 26, 2018, granted, now 10,593,690, issued on Mar. 17, 2020.
Application 16/046,852 is a continuation of application No. PCT/CN2018/077908, filed on Mar. 2, 2018.
Claims priority of application No. 201710135655.3 (CN), filed on Mar. 8, 2017.
Prior Publication US 2023/0363169 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/30 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2224/08146 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a staircase region comprising a first stack and a second stack, wherein:
the first stack is disposed on the substrate and comprises first and second dielectric layers arranged alternately in a vertical direction; and
the second stack is disposed on the substrate and comprises conductor layers and third dielectric layers arranged alternately in the vertical direction;
a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, wherein the barrier structure has an unclosed shape; and
a through array contact extending vertically through the first stack to the substrate.