US 12,137,567 B2
Interconnect structure of three-dimensional memory device
Zhenyu Lu, Hubei (CN); Lidong Song, Hubei (CN); Yongna Li, Hubei (CN); Feng Pan, Hubei (CN); Steve Weiyi Yang, Hubei (CN); and Wenguang Shi, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Wuhan (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Oct. 26, 2020, as Appl. No. 17/080,443.
Application 17/080,443 is a division of application No. 16/046,873, filed on Jul. 26, 2018, granted, now 10,930,663.
Application 16/046,873 is a continuation of application No. PCT/CN2018/077741, filed on Mar. 1, 2018.
Claims priority of application No. 201710134788.9 (CN), filed on Mar. 8, 2017.
Prior Publication US 2021/0043643 A1, Feb. 11, 2021
Int. Cl. H10B 43/50 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 24/05 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H01L 2224/05009 (2013.01); H01L 2224/0557 (2013.01); H10B 41/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) NAND memory device, comprising:
forming an alternating dielectric stack comprising a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer;
forming a first staircase structure in the alternating dielectric stack;
forming a channel structure and a barrier structure each extending vertically through the alternating dielectric stack, wherein the barrier structure separates the alternating dielectric stack into a first portion surrounded by the barrier structure, and a second portion comprising the first staircase structure;
forming a slit;
replacing, through the slit, first dielectric layers in the second portion of the alternating dielectric stack with conductor layers to form an alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs;
forming a slit structure by depositing a conductor in the slit;
forming a first contact layer comprising a plurality of first contacts, wherein the plurality of first contacts flush with one another at a respective first end of each of the first contacts;
forming a second contact layer comprising a plurality of second contacts, wherein the second contact layer is above and different from the first contact layer, wherein each of (i) a conductor layer of the alternating conductor/dielectric stack in the first staircase structure, (ii) the channel structure, and (iii) the slit structure is in contact with a respective second end of the plurality of first contacts, and wherein the plurality of second contacts flush with one another at a respective first end and a respective second end of each of the plurality of second contacts, wherein each of the plurality of second contacts is in contact with a respective one of the plurality of first contacts; and
forming an interconnect conductor layer above the second contact layer, wherein each of (i) a top conductor layer of the alternating conductor/dielectric stack in the first staircase structure, (ii) the channel structure, and (iii) the slit structure is connected to the interconnect conductor layer by a corresponding first contact and a respective one of the plurality of second contacts via a conducting material.