US 12,137,561 B2
Semiconductor memory device and manufacturing method thereof
Sung-Lae Oh, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Sep. 14, 2021, as Appl. No. 17/474,579.
Application 17/342,981 is a division of application No. 16/515,922, filed on Jul. 18, 2019, granted, now 11,063,061, issued on Jul. 13, 2021.
Application 17/474,579 is a continuation in part of application No. 17/342,981, filed on Jun. 9, 2021, granted, now 11,563,030.
Claims priority of application No. 10-2018-0142264 (KR), filed on Nov. 19, 2018.
Prior Publication US 2021/0408041 A1, Dec. 30, 2021
Int. Cl. H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/022 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/528 (2013.01); H10B 43/40 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first stack including a plurality of conductive layers and a plurality of first interlayer insulating layers alternately stacked on a substrate;
a second stack including a plurality of sacrificial layers and a plurality of second interlayer insulating layers alternately stacked on the substrate;
a plurality of stepped grooves defined at different depths in the first stack; and
an opening defined in the second stack, and having, on a sidewall thereof, a plurality of steps which have a same height as differences in depth between the plurality of stepped grooves,
wherein the plurality of first interlayer insulating layers and the plurality of second interlayer insulating layers are formed of a same insulating material, and
the plurality of sacrificial layers are formed of an insulating material which has a different etching selectivity from the plurality of first interlayer insulating layers and the plurality of second interlayer insulating layers.