| CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
|
1. A semiconductor device comprising:
a substrate having a first region, a second region, and a third region;
gate electrodes stacked on the substrate and spaced apart from each other in the first region and the second region, the gate electrodes extending in a first direction to have a stepped shape in the third region;
interlayer insulating layers alternately stacked with the gate electrodes;
channel structures passing through the gate electrodes in the first region and the channel structures including a gate dielectric layer comprising a tunneling layer, a charge storage layer, and a blocking layer, and a channel layer comprising a semiconductor material;
first dummy structures passing through the gate electrodes in the second region, the first dummy structures disposed adjacent to the first region, and respectively including a dummy dielectric layer comprising the tunneling layer, the charge storage layer, and the blocking layer, and a dummy channel layer comprising the semiconductor material;
second dummy structures passing through the gate electrodes in the second region, the second dummy structures disposed adjacent to the third region, and having different shapes from the first dummy structures; and
support structures passing through the gate electrodes in the third region,
wherein a size of each of the second dummy structures is larger than a size of each of the support structures,
wherein the gate electrodes stacked on the substrate do not have a stepped shape in the first region and the second region.
|