CPC H10B 43/10 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/50 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/50 (2023.02)] | 7 Claims |
1. A semiconductor memory device comprising:
a memory string extending in a first direction perpendicular to a substrate, the memory string having a first select transistor and memory cell transistors connected in series;
electrodes stacked in the first direction and extending in a second direction, the electrodes having a first select electrode connected to the first select transistor and control electrodes connected to the memory cell transistors;
a first separation portion extending in the first direction and the second direction, the first select electrode and the control electrodes being separated by the first separation portion; and
a second separation portion extending in the first direction and the second direction, the first select electrode being separated by the second separation portion in a third direction crossing the first direction and the second direction, a part of the control electrodes being separated by the second separation portion in the third direction.
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