| CPC H10B 41/35 (2023.02) [G11C 16/0433 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 29/42328 (2013.01); H10B 41/10 (2023.02); G11C 16/08 (2013.01); G11C 16/24 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a semiconductor substrate;
a first well supported by the semiconductor substrate and structured to include a first active region and doped to exhibit a first conductive type;
a second well supported by the semiconductor substrate and arranged at a side of the first well, the second well structured to include a second active region and doped to exhibit a second conductive type different from the first conductive type;
a third well supported by the semiconductor substrate and arranged at a side of the second well, the third well structured to include a third active region and doped to exhibit the first conductive type of the first well;
a floating gate supported by the semiconductor substrate and positioned to overlap with the first active region, the second active region and the third active region; and
a selection gate supported by the semiconductor substrate and positioned to overlap with the second active region and arranged at a side of the floating gate,
wherein a second overlapping area between the second active region and the floating gate is larger than a third overlapping area between the third active region and the floating gate, and
wherein a line width of the floating gate overlapping with the first active region, a line width of the floating gate overlapping with the second active region and a line width of the floating gate overlapping with the third active region are uniform.
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