	US 12,137,555 B2
	Semiconductor devices including stack structure having gate region and insulating region
Geunwon Lim, Yongin-si (KR); and Seokcheon Baek, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 7, 2023, as Appl. No. 18/348,521.
Application 18/348,521 is a continuation of application No. 17/685,692, filed on Mar. 3, 2022, granted, now 11,744,066.
Application 17/685,692 is a continuation of application No. 16/856,560, filed on Apr. 23, 2020, granted, now 11,271,003, issued on Mar. 8, 2022.
Claims priority of application No. 10-2019-0086900 (KR), filed on Jul. 18, 2019.
Prior Publication US 2023/0354597 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 41/27 (2023.01); G11C 5/02 (2006.01); H01L 29/788 (2006.01)

CPC H10B 41/27 (2023.02) [G11C 5/025 (2013.01); H01L 29/788 (2013.01)]

20 Claims

1. A semiconductor device, comprising:

a peripheral circuit structure;

an upper substrate vertically overlaps the peripheral circuit structure;

a stack structure on the upper substrate, and including a first stack portion and a second stack portion; and

a vertical memory structure penetrating through the first stack portion of the stack structure,

wherein the first stack portion includes interlayer insulating layers and conductive layers alternately stacked in a vertical direction,

wherein the second stack portion includes first insulating layers and second insulating layers alternately stacked in the vertical direction,

wherein a material of the first insulating layers is different from a material of the second insulating layers,

wherein the second insulating layers include a first layer and a second layer on the first layer,

wherein the second layer includes a first portion, a second portion, and a third portion between the first portion and the second portion, and

wherein a thickness of each of the first and second portions is greater than a thickness of the third portion.