| CPC H10B 41/27 (2023.02) [H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H10B 43/27 (2023.02)] | 6 Claims |

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1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stack comprises a staircase region in which lateral extents of the electrically conductive layers decrease with a vertical distance from the substrate;
memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements;
etch stop plates located in the staircase region, and overlying an end portion of a respective one of the electrically conductive layers, wherein the etch stop plates comprise tungsten carbonitride; and
contact via structures located in the staircase region, vertically extending through a respective one of the etch stop plates, and contacting the respective one of the electrically conductive layers.
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