US 12,137,553 B2
Memory array and method used in forming a memory array
Sidhartha Gupta, Boise, ID (US); Naveen Kaushik, Boise, ID (US); and Pankaj Sharma, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 5, 2021, as Appl. No. 17/395,211.
Prior Publication US 2023/0039621 A1, Feb. 9, 2023
Int. Cl. H10B 41/27 (2023.01); H01L 23/538 (2006.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [H01L 23/5384 (2013.01); H10B 43/27 (2023.02)] 29 Claims
OG exemplary drawing
 
1. A method used in forming a memory array, comprising:
forming a stack comprising vertically-alternating insulative tiers and conductive tiers, channel-material strings of memory-cell strings extending through the insulative and conductive tiers;
forming conductive vias above and individually electrically coupled to individual of the channel-material strings, insulating material being laterally-between immediately-adjacent of the conductive vias;
vertically removing at least some of the insulating material to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias;
forming insulative material laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space, the covered void-space in a vertical cross-section being widest at a top portion thereof than at a bottom portion thereof; and
forming digitlines above and that are individually electrically coupled to a plurality of individual of the conductive vias there-below.