US 12,137,550 B2
Semiconductor structure with a first lower electrode layer and a second lower electrode layer and method for manufacturing same
Deyuan Xiao, Hefei (CN); and Lixia Zhang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 11, 2022, as Appl. No. 17/669,544.
Application 17/669,544 is a continuation of application No. PCT/CN2021/120429, filed on Sep. 24, 2021.
Claims priority of application No. 202110807121.7 (CN), filed on Jul. 16, 2021.
Prior Publication US 2023/0019891 A1, Jan. 19, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 29/786 (2006.01)
CPC H10B 12/315 (2023.02) [H01L 29/78642 (2013.01); H01L 29/7869 (2013.01); H10B 12/033 (2023.02); H10B 12/05 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base and a storage unit located on the base, the storage unit comprising:
a first dielectric layer and a metal bit line located in the first dielectric layer, the first dielectric layer exposing a surface of the metal bit line;
a semiconductor channel, located on a partial surface of the metal bit line, the semiconductor channel facing a bottom surface of the metal bit line and being electrically connected to the metal bit line;
a word line, disposed surrounding a partial region of the semiconductor channel;
a second dielectric layer, located between the metal bit line and the word line, and further located on a side of the word line away from the base;
a first lower electrode layer and a second lower electrode layer, stacked on a top surface of the semiconductor channel away from the metal bit line, the first lower electrode layer contacting the top surface of the semiconductor channel;
an upper electrode layer, located on a top surface of the second lower electrode layer, and surrounding the first lower electrode layer and the second lower electrode layer; and
a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and further located between the upper electrode layer and the second lower electrode layer;
wherein the capacitor dielectric layer comprises:
a first capacitor dielectric layer, covering a side surface of the first lower electrode layer;
a second capacitor dielectric layer, covering a top surface of the first lower electrode layer exposed from the second lower electrode layer;
a third capacitor dielectric layer, covering the top surface and a side surface of the second lower electrode layer; and
a fourth capacitor dielectric layer, connected to a bottom surface of the first capacitor dielectric layer, and extending in a direction away from an axis of the first lower electrode layer perpendicular to a surface of the base; and the upper electrode layer is further located on a surface of the fourth capacitor dielectric layer.