CPC H10B 12/30 (2023.02) [G11C 5/025 (2013.01); G11C 5/10 (2013.01); G11C 11/407 (2013.01); H10B 12/03 (2023.02)] | 32 Claims |
1. A microelectronic device, comprising:
array regions individually comprising:
memory cells comprising access devices and storage node devices;
digit lines coupled to the access devices and extending in a first direction;
word lines coupled to the access devices and extending in a second direction orthogonal to the first direction; and
control logic devices over and in electrical communication with the memory cells; and
capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction, the capacitor regions individually comprising:
additional control logic devices vertically overlying the memory cells; and
capacitor structures within horizontal boundaries of the additional control logic devices.
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