| CPC H10B 10/12 (2023.02) [G06F 30/392 (2020.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); G03F 1/70 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
first and second write-word lines; and
first and second memory cells, each of which includes:
a latch;
a first pass gate coupled between an input node of the latch and a bit line;
a second pass gate coupled between an output node of the latch and a bit_bar line;
the latch and the first and second pass gates being in a transistor layer; and
gate electrodes of the first and second pass gates being coupled to a corresponding one of the first or second write-word lines;
gate lines which are correspondingly over the transistor layer and which have corresponding long axes extending in a first direction;
for each latch, gate electrodes of transistors included therein being coupled correspondingly to the gate lines; and
the gate lines being organized into first, second, third and fourth sets which are non-overlapping relative to a second direction substantially perpendicular to the first direction, each set including two or more of the gate lines which have substantially collinear long axes; and
each of the first and second memory cells being coupled to a corresponding one of the gate lines in each of the first, second, third and fourth sets such that each of the first and second memory cells is a four contacted poly pitch memory cell; and
power grid lines for the transistors and the pass gates being underneath the transistor layer.
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