CPC H04W 72/02 (2013.01) [H04L 5/0012 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 72/20 (2023.01)] | 20 Claims |
1. A baseband processor, comprising:
a memory; and
processing circuitry in communication with the memory and configured to perform operations comprising:
receiving cellular sidelink control channel configuration information, wherein the cellular sidelink control channel configuration information indicates a cellular sidelink control channel configuration that includes frequency hopping and multi-beam diversity and is based, at least in part, on one or more preferred cellular sidelink control channel configuration parameters; and
performing cellular sidelink communication with a wireless device using the cellular sidelink control channel configuration that includes frequency hopping and multi-beam diversity, wherein performing the cellular sidelink communication includes:
transmitting on one or more lowest indexed frequency resources using a first beam for a first number of symbols of a time slot; and
transmitting on one or more of highest indexed frequency resources using a second beam for a second number of subsequent symbols of the time slot.
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