US 12,137,419 B2
Power management integrated circuit, power management method, mobile device and clock adjusting method
Junghun Heo, Suwon-si (KR); Youngduk Kim, Hwaseong-si (KR); Joonseok Kim, Seoul (KR); and Dongsuk Shin, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 4, 2023, as Appl. No. 18/143,105.
Application 18/143,105 is a continuation of application No. 17/408,700, filed on Aug. 23, 2021, granted, now 11,653,308.
Application 17/408,700 is a continuation of application No. 16/537,869, filed on Aug. 12, 2019, granted, now 11,122,513, issued on Sep. 14, 2021.
Application 16/537,869 is a continuation of application No. 14/793,381, filed on Jul. 7, 2015, granted, now 10,383,062, issued on Aug. 13, 2019.
Claims priority of application No. 10-2014-0111717 (KR), filed on Aug. 26, 2014.
Prior Publication US 2023/0276367 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); H04W 52/02 (2009.01)
CPC H04W 52/0287 (2013.01) [G06F 1/32 (2013.01); H04W 52/0261 (2013.01); Y02D 30/70 (2020.08)] 20 Claims
OG exemplary drawing
 
1. A system-on-chip (SOC) comprising:
a clock divider configured to receive a source clock and to generate an operating clock by dividing the source clock, the source clock being externally provided;
a central processing unit (CPU) configured to receive the operating clock and to operate in response to the operating clock; and
an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided, wherein the interrupt signal indicates a state transition to the CPU,
wherein the clock divider is further configured to receive the one of the first alarm signal and the second alarm signal, to generate the operating clock with a first frequency in response to receiving the first alarm signal, and to generate the operating clock with a second frequency in response to receiving the second alarm signal, the second frequency being less than the first frequency, wherein the operating clock and the interrupt signal are separate signals.