CPC H04W 24/04 (2013.01) [H04W 24/10 (2013.01); H04W 28/06 (2013.01); H04W 72/51 (2023.01); H04W 72/54 (2023.01); H04W 84/12 (2013.01)] | 20 Claims |
1. A device, the device comprising processing circuitry coupled to storage, the processing circuitry configured to:
generate a first control identifier of a medium access control (MAC) frame indicative of a presence of an operating mode (OM) control subfield in the MAC frame;
generate a second control identifier of the MAC frame indicative of a presence of an extremely high throughput (EHT) OM control subfield in the MAC frame;
set three bits of a receive number of spatial streams (RX NSS) subfield of the OM control subfield and one bit of a RX NSS extension subfield of the EHT OM control subfield to indicate more than eight RX NSS;
set three bits of a transmit number of spatial streams (TX NSTS) subfield of the OM control subfield and one bit of a TX NSTS extension subfield of the EHT OM control subfield to indicate more than eight TX NSTS;
set two bits of a channel width subfield of the OM subfield and one bit of a channel width extension subfield of the EHT OM subfield to indicate a bandwidth greater than 80 MHz; and
transmit the MAC frame comprising a high throughput (HT) control field comprising the OM control subfield and the EHT OM control subfield.
|