US 12,137,296 B1
Optimized pixel design for mitigating MIM image lag
Yuanliang Liu, San Jose, CA (US); Bill Phan, Sunnyvale, CA (US); and Duli Mao, Sunnyvale, CA (US)
Assigned to OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Apr. 11, 2023, as Appl. No. 18/298,975.
Int. Cl. H04N 25/771 (2023.01); H04N 25/59 (2023.01)
CPC H04N 25/771 (2023.01) [H04N 25/59 (2023.01)] 20 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a photodiode configured to photogenerate one or more image charges in response to incident light;
a floating diffusion coupled to receive the one or more image charges from the photodiode;
a transfer transistor coupled between the photodiode and the floating diffusion to transfer the one or more image charges from the photodiode to the floating diffusion;
a reset transistor coupled between a pixel voltage source and the floating diffusion, wherein the reset transistor is configured to be switched in response to a reset control signal;
a lateral overflow integration capacitor (LOFIC) network coupled to the floating diffusion, a first bias voltage source, and a second bias voltage source, the LOFIC network comprising:
a first LOFIC coupled between the floating diffusion and the first bias voltage source; and
a second LOFIC coupled between the floating diffusion and the second bias voltage source;
wherein the first LOFIC is configured to be forward biased and the second LOFIC is configured to be reverse biased at an end of an integration period, and
wherein charge discharged from the first LOFIC and charge discharged from the second LOFIC compensate each other during a readout period.