US 12,137,295 B2
Pixel circuit selecting to output time difference data or image data
Ren-Chieh Liu, Hsin-Chu County (TW); and Yi-Cheng Chiu, Hsin-Chu County (TW)
Assigned to PIXART IMAGING INC., Hsin-Chu County (TW)
Filed by PixArt Imaging Inc., Hsin-Chu County (TW)
Filed on Aug. 18, 2023, as Appl. No. 18/235,370.
Application 18/235,370 is a division of application No. 17/395,527, filed on Aug. 6, 2021, granted, now 11,812,176.
Application 17/395,527 is a continuation in part of application No. 17/009,417, filed on Sep. 1, 2020, granted, now 11,290,671.
Prior Publication US 2023/0396896 A1, Dec. 7, 2023
Int. Cl. H04N 25/767 (2023.01); H01L 27/146 (2006.01)
CPC H04N 25/767 (2023.01) [H01L 27/14612 (2013.01); H01L 27/14643 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a photodiode, configured to generate light energy;
a first temporal circuit, comprising:
a first capacitor having a first end coupled to the photodiode;
a second temporal circuit, comprising:
a second capacitor having a first end coupled to the photodiode;
a first comparator, comprising:
a first input transistor, arranged inside the first temporal circuit and connected to a second end of the first capacitor; and
a second input transistor, arranged outside the first temporal circuit and shared with other pixel circuits;
a second comparator, comprising:
a third input transistor, arranged inside the second temporal circuit and connected to a second end of the second capacitor; and
a fourth input transistor, arranged outside the second temporal circuit and shared with the other pixel circuits;
a transfer transistor, connected between the photodiode and the first end of the first capacitor as well as the first end of the second capacitor, and configured to transfer the light energy to the first temporal circuit in a first interval and a second interval, and transfer the light energy to the second temporal circuit in the second interval; and
a reset transistor, connected between the transfer transistor and the first end of the first capacitor as well as the first end of the second capacitor, wherein
the first temporal circuit further comprises a second transistor connected between the first capacitor and the first input transistor,
the second temporal circuit further comprises a second transistor connected between the second capacitor and the third input transistor, and
the second transistor of the first temporal circuit is not conducted in the second interval, and the second transistor of the second temporal circuit is not conducted in the first interval.