US 12,137,169 B2
Low latency post-quantum signature verification for fast secure-boot
Santosh Ghosh, Hillsboro, OR (US); Vikram Suresh, Portland, OR (US); Sanu Mathew, Portland, OR (US); Manoj Sastry, Portland, OR (US); Andrew H. Reinders, Portland, OR (US); Raghavan Kumar, Hillsboro, OR (US); and Rafael Misoczki, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,911.
Application 17/854,911 is a continuation of application No. 16/456,034, filed on Jun. 28, 2019, granted, now 11,405,213.
Prior Publication US 2022/0337421 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/32 (2006.01); H04L 9/00 (2022.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); H04L 9/30 (2006.01)
CPC H04L 9/3236 (2013.01) [H04L 9/0643 (2013.01); H04L 9/0852 (2013.01); H04L 9/0877 (2013.01); H04L 9/30 (2013.01); H04L 9/50 (2022.05)] 13 Claims
OG exemplary drawing
 
1. An apparatus comprising:
host processor circuitry; and
a hardware accelerator, coupled to the host processor circuitry, including a SHAKE hardware accelerator, the hardware accelerator comprising:
memory to store a set of Extended Merkle Signature Scheme (XMSS) inputs associated with multiple XMSS operations,
XMSS verification circuitry to manage multiple XMSS verification functions associated with the multiple XMSS operations, wherein
a first XMSS verification function is a public key generation to be performed by an execution of a chain function that is to use the SHAKE hardware accelerator to generate public key components,
a second XMSS verification function is L-tree computation that is to combine the public key components by using the SHAKE hardware accelerator,
a third XMSS verification function is a tree-hash computation that is to use an output of the L-tree computation and the SHAKE hardware accelerator to generate a root node, wherein the SHAKE hardware accelerator comprises a 1600-bit state register used to receive the set of XMSS inputs including one or more of a first set of inputs for each chain function, a second set of inputs for hashes involved in an L-Tree computation, a third set of inputs for a Merkle tree root node computation, or a 256-bit message input.