| CPC H04L 7/0087 (2013.01) | 20 Claims |
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1. An electronic device, comprising:
clock recovery circuit configured to receive a data signal and recover a clock signal from the data signal, the data signal carrying a stream of data bits according to a reference clock frequency; and
a bandwidth controller coupled to the clock recovery circuit, the bandwidth controller configured to control the clock recovery circuit to start with a pull-in bandwidth, settle at a target bandwidth, and apply an intermediate bandwidth between the pull-in bandwidth and target bandwidth, wherein the intermediate bandwidth is greater than the target bandwidth and less than the pull-in bandwidth.
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