US 12,136,996 B2
Method and apparatus for low power chip-to-chip communications with constrained ISI ratio
Amin Shokrollahi, Préverenges (CH); Ali Hormati, Ecublens Vaud (CH); and Roger Ulrich, Bern (CH)
Assigned to KANDOU LABS, S.A., Saint-Sulpice (CH)
Filed by Kandou Labs, S.A., Lausanne (CH)
Filed on Jun. 20, 2023, as Appl. No. 18/337,934.
Application 18/337,934 is a continuation of application No. 17/336,082, filed on Jun. 1, 2021, granted, now 11,683,113.
Application 17/336,082 is a continuation of application No. 16/504,440, filed on Jul. 8, 2019, granted, now 11,025,359, issued on Jun. 1, 2021.
Application 16/504,440 is a continuation of application No. 15/019,868, filed on Feb. 9, 2016, granted, now 10,348,436, issued on Jul. 9, 2019.
Application 15/019,868 is a continuation of application No. 14/816,899, filed on Aug. 3, 2015, granted, now 9,258,154, issued on Feb. 9, 2016.
Application 14/816,899 is a continuation of application No. 14/612,241, filed on Feb. 2, 2015, granted, now 9,100,232, issued on Aug. 4, 2015.
Claims priority of provisional application 61/934,804, filed on Feb. 2, 2014.
Prior Publication US 2023/0336266 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/03 (2006.01); H04J 13/00 (2011.01); H04L 25/02 (2006.01); H04L 25/14 (2006.01); H04L 25/49 (2006.01)
CPC H04J 13/004 (2013.01) [H04L 25/0272 (2013.01); H04L 25/0276 (2013.01); H04L 25/03343 (2013.01); H04L 25/14 (2013.01); H04L 25/4919 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
obtaining a set of input signals;
generating a set of output signals for transmission in parallel over N wires of a multi-wire channel, wherein N is an even integer greater than 2, the set of output signals corresponding to a weighted summation of a plurality of sub-channel vectors of an ODVS code, each sub-channel vector weighted by a corresponding input signal of the set of input signals, wherein the plurality of sub-channel vectors comprise (i) at least one pair-wise sub-channel vector having sub-channel vector elements on a differential pair of wires, (ii) at least two sub-channel vectors having sub-channel vector elements on respective groups of N/2 wires, and (iii) one sub-channel vector having sub-channel vector elements on all N wires; and
transmitting each output signal as an analog signal on a respective wire of the multi-wire channel.