US 12,136,931 B2
Semiconductor device, analog-to-digital converter and analog-to-digital converting method
Pratama Fajarmega, Tokyo (JP); Tatsuo Nishino, Tokyo (JP); and Takehiro Shimizu, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Nov. 9, 2022, as Appl. No. 17/983,576.
Claims priority of application No. 2021-182896 (JP), filed on Nov. 9, 2021.
Prior Publication US 2023/0147156 A1, May 11, 2023
Int. Cl. H03M 1/46 (2006.01); H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/38 (2006.01); H03M 1/76 (2006.01)
CPC H03M 1/462 (2013.01) [H03M 1/0636 (2013.01); H03M 1/069 (2013.01); H03M 1/1009 (2013.01); H03M 1/38 (2013.01); H03M 1/468 (2013.01); H03M 1/765 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a port to which an analog input signal is input; and
a successive-approximation analog-to-digital converter configured to perform a process of sampling the analog input signal input to the port and a successive-approximation process, execute an analog-to-digital conversion process, and output a digital output signal,
wherein the analog-to-digital converter comprises:
an upper DAC configured to perform a digital-to-analog conversion corresponding to an upper bit of the digital output signal;
a redundant DAC configured to perform a digital-to-analog conversion corresponding to a redundant bit added to a bit of the upper DAC;
a lower DAC configured to perform a digital-to-analog conversion corresponding to a lower bit of the digital output signal;
a comparator configured to compare a comparative reference voltage and output voltages of the upper DAC, the redundant DAC and the lower DAC;
a control circuit configured to control successive approximations by the upper DAC, the redundant DAC and the lower DAC based on a comparison result of the comparator, and generate the digital output signal; and
a correction circuit configured to correct the digital output signal, and
wherein the correction circuit comprises:
an error correction circuit configured to correct an error of the upper bit with the redundant bit; and
an averaging circuit configured to calculate an average value of conversion values of a plurality of the lower bits supplied multiple times.