| CPC H03M 1/1009 (2013.01) | 20 Claims |
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1. An analog-to-digital converter (ADC) apparatus, comprising:
an ADC comprising sub-ADCs, wherein each sub-ADC of the ADC is configured to receive an input signal, configured to receive a clock signal, and configured to produce a sub-ADC output signal,
a digital mixer coupled to the ADC, the digital mixer comprising sub-mixers, wherein each sub-mixer of the digital mixer is configured to receive the respective sub-ADC output signal, configured to receive a controlled oscillator signal value, and configured to produce a sub-mixer output signal; and
a combiner coupled to the digital mixer, wherein the combiner is configured to combine the sub-mixer output signals and configured to produce a combined output signal,
wherein:
the clock signal for each sub-ADC of the ADC is associated with a representation of a timing skew value;
for each sub-ADC of the ADC, the respective timing skew value represents a timing error;
each timing skew value is a value in time;
for each sub-mixer of the digital mixer, the controlled oscillator signal value is determined using a phase skew value;
each phase skew value is an offset value in phase and is not a value in time;
each phase skew value is determined based on the respective timing skew value;
each phase skew value in a phase domain is for compensating the respective timing skew value in a time domain;
the controlled oscillator signal values are determined in real time after the ADC receives the input signal; and
the controlled oscillator signal values are different from pre-existing controlled oscillator signal values determined or provided before the ADC receives the input signal.
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