CPC H03L 7/087 (2013.01) [H03L 7/093 (2013.01); H03L 7/0991 (2013.01)] | 20 Claims |
1. A phase-locked loop (PLL) circuit, comprising:
an oscillator configured to provide a clock signal;
a frequency search circuit configured to:
measure a first frequency of the clock signal, the first frequency associated with a first code;
measure a second frequency of the clock signal, the second frequency associated with a second code;
determine, based on the first frequency, the second frequency, the first code, and the second code, a slope value;
determine a third code based on the slope value and a target frequency; and
provide the third code to the oscillator; and
an analog control loop configured to control the oscillator to cause a frequency of the clock signal to converge to the target frequency.
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