US 12,136,925 B2
Clock synthesizer
Wei Shuo Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 17, 2023, as Appl. No. 18/301,850.
Application 18/301,850 is a continuation of application No. 17/566,156, filed on Dec. 30, 2021, granted, now 11,632,115.
Claims priority of provisional application 63/188,727, filed on May 14, 2021.
Prior Publication US 2023/0370071 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03L 7/083 (2006.01); H03K 3/017 (2006.01); H03L 7/081 (2006.01); H03L 7/099 (2006.01); H03L 7/187 (2006.01)
CPC H03L 7/083 (2013.01) [H03K 3/017 (2013.01); H03L 7/0818 (2013.01); H03L 7/0998 (2013.01); H03L 7/187 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit comprising:
a phase interpolator operative to receive a clock signal having a first phase value and provide an output clock signal having a second phase value;
a first Direct Current (DC) sampler operative to determine an average DC voltage value of inverted output clock signal;
a second DC sampler operative to determine an average DC voltage value of the output clock signal;
an error amplifier connected to the first DC sampler and the second DC sampler, wherein the error amplifier is operative to determine a difference between the average DC voltage value of the inverted output clock signal and the average DC voltage of the clock signal; and
a voltage/current alternator connected to an output of the error amplifier, wherein the voltage/current alternator is operative to adjust a duty cycle of the output clock signal based on the difference between the average DC voltage value of the inverted output clock signal and the average DC voltage of the output clock signal.