US 12,136,924 B2
Digitally calibrated programmable clock phase generation circuit
Robert W Kim, Aliso Viejo, CA (US)
Assigned to AyDeeKay LLC, Aliso Viejo, CA (US)
Filed by AyDeeKay LLC, Aliso Viejo, CA (US)
Filed on Oct. 3, 2023, as Appl. No. 18/376,420.
Application 18/376,420 is a continuation of application No. 18/126,889, filed on Mar. 27, 2023, granted, now 11,831,322.
Application 18/126,889 is a continuation of application No. 17/555,840, filed on Dec. 20, 2021, granted, now 11,641,206.
Claims priority of provisional application 63/134,955, filed on Jan. 7, 2021.
Prior Publication US 2024/0030925 A1, Jan. 25, 2024
Int. Cl. H03L 7/081 (2006.01); H03L 7/099 (2006.01); H03M 1/10 (2006.01)
CPC H03L 7/0814 (2013.01) [H03L 7/0995 (2013.01); H03M 1/1061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a generating circuit configured to provide an edge clock having a target phase within a clock period of an input clock, wherein the generating circuit does not include a delay locked loop (DLL), and
wherein the generating circuit is periodically calibrated.