US 12,136,923 B2
Superconducting circuit multi-chip synchronization system
Jeffrey S. Hall, Annapolis, MD (US); Jonathan D. Egan, Hanover, MD (US); and Joseph A. Payne, Cooksville, MD (US)
Assigned to NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US)
Filed by Jeffrey S. Hall, Annapolis, MD (US); Jonathan D. Egan, Hanover, MD (US); and Joseph A. Payne, Cooksville, MD (US)
Filed on Mar. 2, 2023, as Appl. No. 18/177,299.
Prior Publication US 2024/0297651 A1, Sep. 5, 2024
Int. Cl. H03L 7/06 (2006.01); G06N 10/40 (2022.01); H03K 3/03 (2006.01); H03K 17/92 (2006.01)
CPC H03L 7/06 (2013.01) [G06N 10/40 (2022.01); H03K 3/0315 (2013.01); H03K 17/92 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A superconducting circuit chip comprising:
first superconducting circuitry that operates based on a clock signal; and
a first ring oscillator configured to receive a synchronization signal from a second ring oscillator associated with another superconducting circuit chip and to provide a first trigger signal to the first superconducting circuitry at a given phase of the clock signal relative to a phase of the clock signal at which a second trigger signal is provided to second superconducting circuitry associated with the other superconducting circuit chip based on the synchronization signal.