US 12,136,922 B2
Integrated resistor network and method for fabricating the same
Oren Shlomo, Haifa (IL)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Infineon Technologies LLC, San Jose, CA (US)
Filed on Nov. 17, 2023, as Appl. No. 18/512,419.
Application 18/512,419 is a continuation of application No. 17/113,501, filed on Dec. 7, 2020, granted, now 11,855,641.
Claims priority of provisional application 63/048,975, filed on Jul. 7, 2020.
Prior Publication US 2024/0162896 A1, May 16, 2024
Int. Cl. G01K 7/18 (2006.01); G01K 7/20 (2006.01); G01R 19/25 (2006.01); G05F 1/648 (2006.01); G11C 7/02 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 7/20 (2006.01); H03K 5/1252 (2006.01); H03K 5/153 (2006.01); H03K 5/19 (2006.01); H03K 5/24 (2006.01); H03K 17/22 (2006.01); H03K 17/24 (2006.01)
CPC H03K 5/1252 (2013.01) [G01K 7/183 (2013.01); G01K 7/20 (2013.01); G01R 19/2506 (2013.01); G05F 1/648 (2013.01); G11C 7/02 (2013.01); G11C 7/1039 (2013.01); G11C 7/14 (2013.01); G11C 7/20 (2013.01); H03K 5/153 (2013.01); H03K 5/19 (2013.01); H03K 5/2472 (2013.01); H03K 17/223 (2013.01); H03K 17/24 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated resistor network comprising:
a resistor ladder including a first number (n) of first integrated resistors coupled in series between a top contact and a bottom contact, with one or more contacts coupled between two adjacent first integrated resistors, wherein n is a natural positive number greater than 2;
a second number of second integrated resistors coupled in parallel with one another, and each having a first terminal directly connected to the bottom contact, wherein the second number is n−1; and
a third number of integrated resistors connected in series between second terminals of the second integrated resistors and the top contact,
wherein a voltage developed across each of the first integrated resistors is VTOP-BOT/n, and wherein VTOP-BOT is a voltage applied between the top contact and the bottom contact.