| CPC H02M 3/07 (2013.01) [H02M 1/0058 (2021.05); H02M 3/158 (2013.01)] | 22 Claims |
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1. A switched capacitor voltage converter circuit configured to convert a first voltage into a second voltage or to convert the second voltage into the first voltage, the switched capacitor voltage converter circuit comprising:
a switched capacitor converter coupled between the first voltage and the second voltage;
a control circuit configured to generate a control signal for controlling the switched capacitor converter to convert the first voltage to the second voltage or to convert the second voltage to the first voltage; and
a zero current estimation circuit, which is coupled to the switched capacitor converter;
wherein the switched capacitor converter includes:
at least one resonant capacitor;
a plurality of switches coupled to the at least one resonant capacitor; and
at least one inductor;
wherein the zero current estimation circuit is coupled to the at least one inductor or to the at least one resonant capacitor, and the zero current estimation circuit is configured to estimate a time point at which a first resonant current is zero during a first process or estimate a time point at which at least one second resonant current is zero during at least one second process according to a voltage difference across two ends of the at least one inductor or according to a voltage difference across two ends of the at least one resonant capacitor, so as to correspondingly generate a zero current estimation signal at a time point which is not later than the time point at which the first resonant current is zero or at a time point which is not later than the time point at which the at least one second resonant current is zero, and the control signal is generated according to the zero current estimation signal;
wherein the control signal generated by the control circuit includes: a first operation signal and at least one second operation signal;
wherein, in the first process, the first operation signal controls a first portion of the plurality of switches, so that the at least one resonant capacitor and a corresponding one of the at least one inductor are connected in series between the first voltage and the second voltage, to form a first current path and to operate in a resonant operation mode;
wherein, in the at least one second process, the at least one second operation signal controls a second portion of the plurality of switches, so that the at least one resonant capacitor and the corresponding one of the at least one inductor are connected in series between the second voltage and a DC potential, to simultaneously form or sequentially form a plurality of second current paths and operate in the resonant operation mode;
wherein the first operation signals and the at least one second operation signals have respective ON periods which do not overlap one another, so that the first process and the at least one second process do not overlap each other;
wherein the first process and the at least one second process are performed in a repeated, alternating manner, so as to convert the first voltage into the second voltage or to convert the second voltage into the first voltage;
wherein the zero current estimation circuit includes:
a voltage detection circuit, which is configured to generate a voltage detection signal according to the voltage difference across the two ends of the at least one inductor, wherein the voltage detection signal is indicative of a positive voltage period wherein the voltage difference across the two ends of the at least one inductor is above zero voltage; and
a timer, which is coupled to an output end of the voltage detection circuit and which is configured to generate the zero current estimation signal according to the voltage detection signal;
wherein the timer includes:
a ramp circuit, which is configured to generate a rising ramp of a ramp signal according to the voltage detection signal during the positive voltage period, and to generate a falling ramp of the ramp signal according to the rising ramp after the positive voltage period ends; and
a comparison circuit, which is configured to compare the ramp signal with a zero current threshold, so as to generate the zero current estimation signal for determining a starting time point and an ending time point of the first process and a starting time point and an ending time point of the at least one second process;
wherein the ramp circuit includes:
a boost circuit, which is configured to increase a voltage across a ramp capacitor from zero during the positive voltage period, so as to generate the rising ramp; and
a buck circuit, which is configured to decrease the voltage across the ramp capacitor after the positive voltage period ends, so as to generate the falling ramp;
wherein an absolute value of a slope of the rising ramp is the same as an absolute value of a slope of the falling ramp.
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