US 12,136,671 B2
Gate-all-around field-effect transistor having source side lateral end portion smaller than a thickness of channel portion and drain side lateral end portion
Jingyun Zhang, Albany, NY (US); Choonghyun Lee, Rensselaer, NY (US); Takashi Ando, Tuckahoe, NY (US); Pouya Hashemi, White Plains, NY (US); and Alexander Reznicek, Troy, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 31, 2021, as Appl. No. 17/566,875.
Application 17/566,875 is a division of application No. 16/147,680, filed on Sep. 29, 2018, granted, now 11,239,359.
Prior Publication US 2022/0123144 A1, Apr. 21, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/161 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A gate-all-around field-effect transistor, comprising:
a vertical stack of nanosheet layers, each of the nanosheet layers including:
a source side lateral end portion,
a drain side lateral end portion having a drain side thickness, and
a channel portion between and integral with the source side lateral end portion and the drain side lateral end portion, wherein the channel portion further comprises:
an end portion integral with the source side lateral end portion and having an end portion thickness; and
a main portion integral with the drain side lateral end portion, integral with the end portion, and having a main portion thickness;
a step formed around the channel portion, between the end portion and the main portion;
wherein the end portion thickness is less than the main portion thickness; and
wherein the main portion thickness is the same as the drain side lateral end portion thickness;
a gate wrapping around and operatively associated with the nanosheet layers, wherein the gate includes a high-k gate dielectric layer and a gate metal layer;
an epitaxial source region adjoining the source side lateral end portions of the nanosheet layers and operatively associated with the nanosheet layers, wherein the source side lateral end portions of the nanosheet layers end at the epitaxial source region; and
an epitaxial drain region adjoining the drain side lateral end portions of the nanosheet layers and operatively associated with the nanosheet layers, wherein the drain side lateral end portions of the nanosheet layers end at the epitaxial drain region,
wherein the channel portion is configured for providing threshold voltage asymmetry.