US 12,136,661 B2
Compact CMOS
James D. Welch, Omaha, NE (US)
Filed by James D. Welch, Omaha, NE (US)
Filed on Oct. 18, 2021, as Appl. No. 17/300,746.
Application 17/300,746 is a continuation in part of application No. 16/974,016, filed on Sep. 8, 2020, granted, now 11,798,946.
Prior Publication US 2023/0117871 A1, Apr. 20, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A compact CMOS structure comprising a region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor,
said compact CMOS structure further comprising at least two channels projecting from electrical contact with said region of material in a semiconductor substrate which forms rectifying junctions with both field induced N and P-type semiconductor, said channels being substantially parallel and adjacent to one another;
said compact CMOS structure further comprising a gate structure offset with respect to said channels by insulating material;
said compact CMOS structure further comprising substantially non-rectifying junctions to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor, and to distal ends of said at least two channels;
said substrate, at least in the regions of said channels being characterized by a selection from the group consisting of:
it is substantially or per se. intrinsic;
it is substantially or per se. compensated;
it contains both N and P-type dopants in unequal concentrations;
such that in use a voltage is applied between the substantially non-rectifying junctions at the distal ends of said at least two channels and a voltage is applied to said gate which, when switched between the voltages applied to the substantially non-rectifying distal ends of said at least two channels, causes a voltage to appear at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor which is inverted, in that when the higher of said voltages applied to the substantially non-rectifying junctions to said distal ends of said at least two channels is applied to said gate, the voltage at the substantially non-rectifying junction to said region of material which forms rectifying junctions with both field induced N and P-type semiconductor is low, and vice-versa.