US 12,136,659 B2
Negative-capacitance and ferroelectric field-effect transistor (NCFET and FE-FET) devices
Te-Yang Lai, Hsinchu (TW); Chun-Yen Peng, Hsinchu (TW); Chih-Yu Chang, Hsinchu (TW); Bo-Feng Young, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,064.
Application 17/521,344 is a division of application No. 16/825,750, filed on Mar. 20, 2020, granted, now 11,171,219.
Application 18/362,064 is a continuation of application No. 17/521,344, filed on Nov. 8, 2021, granted, now 11,817,489.
Prior Publication US 2023/0378310 A1, Nov. 23, 2023
Int. Cl. H01L 29/51 (2006.01); H01L 21/266 (2006.01); H01L 21/28 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/516 (2013.01) [H01L 21/28185 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 29/42364 (2013.01); H01L 29/517 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 21/266 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/823878 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a gate dielectric stack disposed over a semiconductor region, forming the gate dielectric stack comprising:
forming an interfacial layer disposed over the semiconductor region, the interfacial layer being non-ferroelectric;
forming a dielectric layer over the interfacial layer;
forming a dopant-source layer over the dielectric layer, wherein the dopant-source layer comprises zirconium oxide; and
forming a ferroelectric dielectric layer by driving dopants from the dopant-source layer into the dielectric layer, a remaining portion of the dopant-source layer remaining from the dopant-source layer after forming the ferroelectric dielectric layer, wherein the ferroelectric dielectric layer comprises a polycrystalline material;
forming a gate electrode over the remaining portion of the dopant-source layer, the gate electrode comprising a conductive layer; and
forming a dielectric mask in direct physical contact with a first top surface of the remaining portion of the dopant-source layer and a second top surface of the gate electrode.