US 12,136,658 B2
Integrated circuit with doped low-k sidewall spacers for gate stacks
Yen-Ting Chen, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); Feng-Cheng Yang, Hsinchu County (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 10, 2023, as Appl. No. 18/349,448.
Application 18/349,448 is a division of application No. 17/107,343, filed on Nov. 30, 2020, granted, now 11,699,737.
Application 16/678,472 is a division of application No. 15/813,742, filed on Nov. 15, 2017, granted, now 10,770,354, issued on Sep. 8, 2020.
Application 17/107,343 is a continuation of application No. 16/678,472, filed on Nov. 8, 2019, granted, now 10,854,726, issued on Dec. 1, 2020.
Prior Publication US 2023/0352554 A1, Nov. 2, 2023
Int. Cl. H01L 29/49 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/4991 (2013.01) [H01L 21/76834 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 21/823864 (2013.01); H01L 29/41725 (2013.01); H01L 29/495 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/66689 (2013.01); H01L 29/78 (2013.01); H01L 21/823425 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate stack disposed on a substrate, the gate stack including a u-shaped gate dielectric layer and a fill material at least partially surrounded by the u-shaped gate dielectric layer;
a first sidewall spacer disposed on a side surface of the gate stack, wherein the first sidewall spacer is formed of a porous low-k dielectric material; and
a second sidewall spacer disposed between the first sidewall spacer and the gate stack such that the second sidewall spacer interfaces with the u-shaped gate dielectric layer,
wherein a bottom surface of the first sidewall spacer is spaced apart from the substrate by a portion of the second sidewall spacer.