US 12,136,646 B2
Coupled polysilicon guard rings for enhancing breakdown voltage in a power semiconductor device
Kuo-Chang Yang, Campbell, CA (US); and Sorin Georgescu, Gilroy, CA (US)
Assigned to POWER INTEGRATIONS, INC., San Jose, CA (US)
Appl. No. 17/615,553
Filed by POWER INTEGRATIONS, INC., San Jose, CA (US)
PCT Filed Jun. 19, 2019, PCT No. PCT/US2019/037962
§ 371(c)(1), (2) Date Nov. 30, 2021,
PCT Pub. No. WO2020/256719, PCT Pub. Date Dec. 24, 2020.
Prior Publication US 2022/0238644 A1, Jul. 28, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/808 (2006.01); H01L 29/861 (2006.01)
CPC H01L 29/0619 (2013.01) [H01L 29/41758 (2013.01); H01L 29/7818 (2013.01); H01L 29/808 (2013.01); H01L 29/861 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first device region;
a second device region;
a drift region between the first device region and the second device regions; and
at least one guard ring comprising a first guard ring and further comprising at least one diode electrically coupled between the first device region and the second device region;
wherein the drift region comprises a first shallow trench isolation (STI) trench aligned with the first guard ring,
wherein the semiconductor device is configured to receive a voltage between the first device region and the second device region,
wherein the at least one diode is configured to provide a leakage current in response to the voltage, and
wherein the at least one guard ring is configured to support an electric field within the drift region in response to the voltage.