US 12,136,644 B2
Process for tuning via profile in dielectric material
Chun Kai Tzeng, Tainan (TW); Cheng Jen Lin, Kaohsiung (TW); Yung-Ching Chao, Gukeng Township (TW); Ming-Da Cheng, Taoyuan (TW); and Mirng-Ji Lii, Sinpu Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 8, 2022, as Appl. No. 18/063,339.
Application 17/140,766 is a division of application No. 16/289,831, filed on Mar. 1, 2019, granted, now 10,910,466, issued on Feb. 2, 2021.
Application 18/063,339 is a continuation of application No. 17/140,766, filed on Jan. 4, 2021, granted, now 11,532,692.
Claims priority of provisional application 62/748,827, filed on Oct. 22, 2018.
Prior Publication US 2023/0107187 A1, Apr. 6, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/10 (2013.01) [H01L 21/31133 (2013.01); H01L 21/31144 (2013.01); H01L 23/5227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a magnetic layer;
a first conductive line and a second conductive line parallel to each other, wherein the first conductive line and the second conductive line are elongated, and the first conductive line comprises:
a first part overlapping the magnetic layer; and
a second part vertically offset from magnetic layer; and
a dielectric layer contacting a top surface of the magnetic layer, and contacting top surfaces and sidewalls of the first conductive line and the second conductive line, wherein in a cross-section that is perpendicular to a lengthwise direction of the first conductive line, the dielectric layer comprises a first portion that has a slanted sidewall, and the first portion of the dielectric layer contacts a sidewall of the first conductive line.