US 12,136,632 B2
Methods of manufacturing electronic structures
Richard Price, Sedgefield (GB); Catherine Ramsdale, Sedgefield (GB); Brian Hardy Cobb, Sedgefield (GB); and Feras Alkhalil, Sedgefield (GB)
Assigned to PRAGMATIC PRINTING LTD., Sedgefield (GB)
Filed by PRAGMATIC PRINTING LTD., Sedgefield (GB)
Filed on Aug. 8, 2023, as Appl. No. 18/231,585.
Application 18/231,585 is a division of application No. 17/315,463, filed on May 10, 2021, granted, now 11,978,744.
Application 17/315,463 is a continuation of application No. 16/497,636, granted, now 11,004,875, issued on May 11, 2021, previously published as PCT/GB2018/050805, filed on Mar. 27, 2018.
Claims priority of application No. 1705270 (GB), filed on Mar. 31, 2017.
Prior Publication US 2023/0387145 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 21/3213 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01)
CPC H01L 27/1251 (2013.01) [H01L 21/02266 (2013.01); H01L 21/02631 (2013.01); H01L 21/0274 (2013.01); H01L 21/2855 (2013.01); H01L 21/30604 (2013.01); H01L 21/32133 (2013.01); H01L 27/1262 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01); H01L 29/401 (2013.01); H01L 29/41733 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method of manufacturing an electronic structure comprising a first Field Effect Transistor (FET) and a second FET, the method comprising:
providing a support;
forming a first source terminal, a first drain terminal, and a first layer or body of semiconductive material supported on the support, the first layer or body of semiconductive material providing a first semiconductive channel connecting the first source terminal to the first drain terminal;
forming a first layer or body of dielectric material over the first layer or body of semiconductive material;
forming a layer or body of conductive material over the first layer or body of dielectric material;
forming a second layer or body of dielectric material over the layer or body of conductive material;
forming a second layer or body of semiconductive material over the second layer or body of dielectric material;
patterning the first and second layers or bodies of semiconductive material, the first and second layers or bodies of dielectric material, and said layer or body of conductive material to uncover portions of the first source and first drain terminals and produce a stack comprising the first semiconductive channel, a portion of the first layer or body of dielectric material over said first channel, a portion of the layer or body of conductive material over said first channel, a portion of the layer or body of second dielectric material over said first channel, and a portion of the second layer or body of semiconductive material over the first channel;
forming at least one further layer or body of dielectric material over the stack to cover the stack and said uncovered portions of the first source and drain terminals;
patterning the at least one further layer or body of dielectric material to form first and second windows through the at least one further layer or body of dielectric material to said portion of the second layer or body of semiconductive material; and
forming a second source terminal comprising a conductive material at least partially filling the first window, and a second drain terminal comprising a conductive material at least partially filling the second window, such that said portion of the second layer or body of semiconductive material provides a second semiconductive channel, connecting the second source terminal to the second drain terminal,
wherein the first FET comprises the first source terminal, the first drain terminal, the first channel, and said portion of the layer or body of conductive material, the second FET comprises the second source terminal, the second drain terminal, the second channel, and said portion of the layer or body of conductive material.