	US 12,136,629 B2
	Thin film transistor, method for manufacturing the same, and semiconductor device
Toshikazu Kondo, Atsugi (JP); and Hideyuki Kishida, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Nov. 15, 2023, as Appl. No. 18/509,468.
Application 13/558,638 is a division of application No. 12/699,080, filed on Feb. 3, 2010, granted, now 8,247,276, issued on Aug. 21, 2012.
Application 18/509,468 is a continuation of application No. 17/313,034, filed on May 6, 2021, granted, now 11,824,062.
Application 17/313,034 is a continuation of application No. 16/809,980, filed on Mar. 5, 2020, granted, now 11,011,549, issued on May 18, 2021.
Application 16/809,980 is a continuation of application No. 16/151,552, filed on Oct. 4, 2018, granted, now 10,586,811, issued on Mar. 10, 2020.
Application 16/151,552 is a continuation of application No. 15/856,685, filed on Dec. 28, 2017, granted, now 10,096,623, issued on Oct. 9, 2018.
Application 15/856,685 is a continuation of application No. 15/238,010, filed on Aug. 16, 2016, granted, now 9,859,306, issued on Jan. 2, 2018.
Application 15/238,010 is a continuation of application No. 14/942,376, filed on Nov. 16, 2015, granted, now 9,443,981, issued on Sep. 13, 2016.
Application 14/942,376 is a continuation of application No. 14/626,150, filed on Feb. 19, 2015, granted, now 9,209,283, issued on Dec. 8, 2015.
Application 14/626,150 is a continuation of application No. 14/148,307, filed on Jan. 6, 2014, granted, now 8,987,822, issued on Mar. 24, 2015.
Application 14/148,307 is a continuation of application No. 13/736,344, filed on Jan. 8, 2013, granted, now 8,629,000, issued on Jan. 14, 2014.
Application 13/736,344 is a continuation of application No. 13/558,638, filed on Jul. 26, 2012, granted, now 8,362,563, issued on Jan. 29, 2013.
Claims priority of application No. 2009-037912 (JP), filed on Feb. 20, 2009.
Prior Publication US 2024/0162234 A1, May 16, 2024
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/477 (2006.01); H01L 29/24 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01)

CPC H01L 27/1225 (2013.01) [H01L 21/02565 (2013.01); H01L 21/02614 (2013.01); H01L 21/0262 (2013.01); H01L 21/02631 (2013.01); H01L 21/477 (2013.01); H01L 27/1214 (2013.01); H01L 27/1222 (2013.01); H01L 27/124 (2013.01); H01L 27/1248 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 29/24 (2013.01); H01L 29/45 (2013.01); H01L 29/458 (2013.01); H01L 29/4908 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/78603 (2013.01); H01L 29/78606 (2013.01); H01L 29/78618 (2013.01); H01L 29/78663 (2013.01); H01L 29/78678 (2013.01); H01L 29/7869 (2013.01); H01L 29/78693 (2013.01); H10K 59/12 (2023.02); H10K 59/1213 (2023.02); H10K 59/123 (2023.02); H01L 21/02554 (2013.01)]

10 Claims

2. A semiconductor device comprising:

a first transistor;

a second transistor;

a capacitor;

a light-emitting element;

a first wiring; and

a second wiring,

wherein one electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and a gate electrode of the second transistor,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the first wiring,

wherein a pixel electrode of the light-emitting element is electrically connected to one of a source electrode and a drain electrode of the second transistor,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second wiring,

wherein the first transistor comprises a channel formation region in a first oxide semiconductor layer,

wherein the second transistor comprises a channel formation region in a second oxide semiconductor layer,

wherein a first insulating layer is under the first oxide semiconductor layer and the second oxide semiconductor layer, the first insulating layer comprising a region as a gate insulating layer of the first transistor and a region as a gate insulating layer of the second transistor,

wherein the first insulating layer comprises a first contact hole, the first contact hole being in a region not overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer, and the capacitor,

wherein a first conductive layer comprises a region as the pixel electrode,

wherein a width in a first direction of the first conductive layer is larger than a width in a second direction of the first conductive layer, the second direction intersecting the first direction,

wherein the first wiring is extending in the first direction,

wherein the first conductive layer and the first wiring overlap with each other,

wherein a second conductive layer is on a same layer as the first conductive layer and separated from the first conductive layer,

wherein the first contact hole and the second conductive layer overlap with each other,

wherein the second wiring is extending in the first direction,

wherein a width in the first direction of the first oxide semiconductor layer is larger than a width in the second direction of the first oxide semiconductor layer,

wherein a width in the first direction of the second oxide semiconductor layer is larger than a width in the second direction of the second oxide semiconductor layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer are between the first wiring and the second wiring,

wherein a second insulating layer is over the first transistor and the second transistor,

wherein the second insulating layer is under the first conductive layer and the second conductive layer,

wherein the second insulating layer comprises a second contact hole between the first oxide semiconductor layer and the second oxide semiconductor layer, and

wherein the second contact hole and the first conductive layer overlap with each other.