US 12,136,618 B2
Three-dimensional memory device with backside source contact
Kun Zhang, Wuhan (CN); Linchun Wu, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Zhiliang Xia, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 6, 2022, as Appl. No. 17/858,695.
Application 17/858,695 is a continuation of application No. 16/881,294, filed on May 22, 2020, granted, now 11,456,290.
Application 16/881,294 is a continuation of application No. PCT/CN2020/084600, filed on Apr. 14, 2020.
Prior Publication US 2022/0336436 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;
a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack;
a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers; and
a source contact in contact with one side of the semiconductor layers away from the memory stack.