CPC H01L 25/16 (2013.01) [H01L 24/24 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/24265 (2013.01); H01L 2224/244 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19103 (2013.01)] | 20 Claims |
1. A chip package, comprising:
an integrated circuit (IC) die;
a package substrate having a die side and a ball side, the package substrate comprising:
a core having a vias disposed therethrough;
build-up layers having a first surface facing the IC die and a second surface disposed on the core; and
package circuitry having routing terminating on the top and bottom surfaces of the package substrate, the routing passing through the vias and the build-up layers;
an integrated passive device (IPD) layer having conductive posts coupled to pillars disposed below the IC die;
a dielectric interconnection layer disposed between the IC die and the first surface of the build-up layers, the dielectric interconnection layer having conductive pillars coupled to and aligned with the conductive posts of the IPD layer; and
an integrated passive device (IPD) disposed at least partially within the IPD layer, the IPD having at least one terminal electrically coupled to the IC die;
wherein the conductive pillars disposed below the IC die, the conductive posts of the IPD layer, and the conductive pillars of the dielectric interconnection layer are linearly aligned with one another to provide straight electrical connections between the package substrate and the IC die, without fanout or re-distribution within the IPD layer and without fanout or re-distribution between the IPD layer and the IC die.
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